The Pixif's hardware is very simple, with almost all of the "special fancy stuff" being done by the PIC's software. I wanted a straightforward interface to the STM32 board and was able to accomplish that by using a normal 4-wire SPI with the addition of two discrete signals. The interface to the host comprises those 6 signals along with power for the PIC. Note that even though the Pixif's PIC operating voltage range is 1.8V to 5.5V, the output level translation hardware constrains the lower voltage to be around 3.3V. So, Pixif VDD greater than 3.3V: OK. Lower, not so much. See the Output Level Translation and Tuning page for more information on what's going on in that area.
Of the two discrete input signals, /Reset gives the host processor ultimate control over the Pixif - for whatever reason, start over at will! ;-)
The second input, /FrameSync, allows the host processor to control the rate at which the Pixif retrieves a set of RGB bytes for the NeoPixels. A Pixif "frame" is the entire set of color byte values for all of the NeoPixels the Pixif is configured to drive. For example, 32 NeoPixels results in a 96-byte frame, 144 NeoPixels yields a 432-byte frame, etc. As shown later in the logic analyzer traces, whenever the Pixif (as the SPI Main) asserts the SPI /SS signal it will merrily clock in whatever's present at the MISO signal until it's received the complete RGB byte frame. (This highlights the importance of DMA support for the SPI Secondary on the host processor so it can spend its time elsewhere.) The Pixif continuously does its SPI operations with interleaved NeoPixel bitstream generation, so the normal rate of /SS assertion is a function of the configured number of pixels. But because the Pixif checks the /FrameSync level before asserting /SS the /FrameSync signal can be used to throttle how often the Pixif retrieves the RGB frame. For example, the logic analyzer traces show operation with a 144-pixel strand and /FrameSync constantly asserted following the Pixif configuration. Instead of being constantly asserted, if /FrameSync is pulsed (low) at 60 Hz the frame rate would be reduced from ~188 Hz to 60 Hz with the SPI /SS being asserted immediately following the /FrameSync pulse. Of course the /FrameSync assertion rate must be lower than what the free-run (/FrameSync constantly asserted) /SS rate would be. But what is that rate? And where did this weird 188 Hz rate come from? Glad you asked...
The bitstream sent to the NeoPixels by the Pixif runs at ~650 kHz. Because the Pixif interleaves the retrieval of the RGB bytes via SPI with generating the NeoPixel bitstream (study those logic analyzer traces!) the overall rate of data transfer is determined by the bitstream rate (~650 kHz), not the SPI clock rate. So, 144 pixels at 24 bits/pixel at 650 kHz yields ~188 Hz. (Note that the SPI clock rate need only be fast enough to keep the bitstream "pipeline" full of the frame's RGB bytes.)
