Flip-Flops

Flip-flops are the basic piece of sequential logic. They effectively store a single binary digit of state. There are a variety of flip-flops available that differ on how that state is manipulated.

Since a flip-flop stores a binary digit it must, by  definition, have 2 states. Furthermore it is bistable, which means it is stable in each state: when is put in a specific state, it will stay in that state until something causes it to change to the other state.

R-S Flip Flop

This Flip-Flop has two inputs that change its state: Reset and Set.

When R goes low, Q goes low and /Q goes high.

When S goes low, Q goes high and /Q goes low.

When both R and S are high the Flip-Flop is stable and doesn't change.

R and S can not be both low at the same time. Both Q and /Q would be high... something about ripped space-time and imploding realities...

An R-S Flip-Flop is simple. We can build one from half of a 7400 NAND gate chip. The circuit below shows how.  Go ahead, build it and play with it. I'll wait.  The pulse input and LED output boards from part 2 are handy for providing pulse input and watching the output of this, but you can hand wire some push-buttons and LEDs (with resistors!). Note that debouncing isn't a concern in this application, since multiple low input pulses have no effect, it's just the first one that counts. Using the I/O boards just means less wiring to do for a quick experiment.

Both R and S are, by default, high. If R goes low, the output of it's NAND gate goes high regardless of the other input (attached to Q). So /Q is high. That means that both inputs of the other NAND gate are high (since S will be high), making it's output (Q) low. That low value feeds back to the R gate so that when R returns to it's resting high value, it's gate's output stays high. If S goes low, the opposite happens with Q going high, making /Q low (since R is also high). The low /Q will hold the output of the S gate high.

Since things happen with R or S are low, they are active-low inputs.  If we wanted the opposite, i.e. active-high inputs, an inverter would be added to each input.

This Flip-Flop is a sequential circuit. It is not, however, a synchronous circuit. The state change happens whenever R or S go low. We can make it synchronous quite simply. What we have to do is gate R and S using another input: the clock. We can use the other two NAND gates for this. 

When the CLK input is low, both of the gating NANDs output high. When CLK is high, the S and R inputs are passed through the gate NANDs and inverted. So if S is high, the set input to the Flip-Flop will be low, setting it.  Similarly with the R input.

Note that because of the inversion done by the gating NANDs, the inputs to the circuit as a whole are now active-high.

Level vs Edge Triggered

The above clocked R-S Flip-Flop is level triggered; this the CLK input being high that is relevant. As long as CLK is high, the R and S inputs can change the state of the Flip-Flop. Sometimes this is fine, but often we want that window of change to be limited to the instant CLK transitions from low to high or as close as possible to it. If CLK stays high, R and S have no effect after the initial change of CLK. This is what we mean when we say the circuit is edge triggered. It's the rising edge of CLK that is relevant. Specifically, it's the values of R and S at the instant the rising edge occurs.

Rising/positive Edge Detector

We can convert the above level triggered circuit into an edge triggered one with an inverter and an AND gate.  

Remember when we first talked about gates. There was mention of the fact that for a gate it takes some small amount of time for the output to respond to a change in inputs(s). That's usually seen as a bad thing, and much work has been done to make this time smaller and smaller (one result of this work is faster computers). This circuit takes advantage of the small delay in the inverter. When CLK goes high, it takes one input of the AND gate high. Now it takes that small amount of time for the output of the inverter to catch up and switch to low (now that its input is high). In that brief time, both inputs of the AND gate are high, and so it's output goes high. When the inverter catches up its output goes low, and so does the output of the AND gate. The result? A brief high pulse on the output of the AND gate whenever the CLK signal switch from low to high.

If we now slap this edge detector on the CLK input of the level triggered Flip-Flop, its R and S inputs are used to effect its state during that brief pulse. We now have an edge triggered R-S Flip-Flop.

Falling/negative edge detector

If we look at the timing diagram above, we see that the pulse is high for the short time both CLK and /CLK are high. A similar thing happens when CLK switches back to low. The /CLK signal lags slightly so there is a period of time when both are low. If we switch the AND gate for a NOR gate we get a short pulse then.  Thus we can make a falling edge detector as well. Given that, we have the choice of triggering out R-S Flip-Flop on the rising or falling edge of CLK.

J-K Flip-Flop

Firstly, it's clocked.

Secondly, instead of the case where both inputs are active being illegal, it causes the state to toggle.

Set and Clear

It's common for a flip-flop to have a way to set Q to either high or low independent of all other inputs. Set will make Q high (and /Q low) regardless of whatever else might be going on. Conversely Clear will set Q to low (and /Q to high). Having Set and Clear both active at the same time is not a valid situation... that thing about holes in space-time and imploding realities...

One way to think about Set and Clear is as a reset that puts the flip-flop into a known initial condition (0 or 1 depending on which signal is used). It can be used and abused in other ways as well, typically to reset a group of flip-flops when certain conditions occur.

As these flip-flops get more complex, we seldom draw out the gate level circuit. Also, flip-flops are easily available packaged into ICs so it is natural to drop them into a design as a unit. The 7473A and 7476A are two example of J-K flip-flops. the '73 has a clear input, while the '76 has set and clear.  Be careful of the '73... it has power & ground pins in unusual locations. The 74107 has the same functionality with power and ground in the usual locations.

The Universal Flip-Flop

The J-K flip-flop has the distinction that it can be used to construct any other flip-flop, much like NAND gates can be used to construct any other type of gate (and by extension, any digital circuit). Because of this, the J-K is sometimes called a universal flip-flop.

T Flip-Flop

This is a simple one. On the active edge of the T input (rising or falling) the flip-flop's state and Q (and /Q) output toggles.

The T flip-flop isn't usually found as is. You can easily make one using a J-K and making both J and K active: connect them to Vcc if they are active high, or to ground if they are active low. In fact, that's usually how you'll find a T flip-flop.

One neat thing about a T flip-flop is that it will divide whatever clock signal you apply to it by 2. You can chain several T flip-flops together to divide the incoming clock by 2, 4, 8, etc.

D Flip-Flop

The D flip-flop is basically a single bit storage cell. In this respect it is little different than any of the other flip-flops we've looked at; it is differentiated by its simplicity. It has a single input D that is used to set the state on the appropriate clock edge. As usual, Q and /Q reflect that state. That's all there is to it.  The 7474 is the canonical D flip-flop.

It provides Set and Clear inputs as described above, and otherwise the state of the flip-flop only changes on the falling clock edge.

Continuing

Now that we know all about flip-flops, we can look at some things we can use them for.

This guide was first published on Apr 20, 2018. It was last updated on Apr 20, 2018. This page (Flip-Flops) was last updated on Nov 16, 2019.