Counters are a fundamental class of sequential circuitry. There can be used anywhere a series of steps is required. E.g. to drive a hardware state machine.
Unlike shift registers that move bits from one flip-flop to another, counters go through a sequence of numbered states; a 4-bit counter will count 0000, 0001, 0010, 0011, 0100, 0110, 0111, and so on. I.e. they count. The simplest way to accomplish this is to chain T flip-flops together:
This will count from 0000 to 1111, and loop back to 0000.
The problem with this design is that each flip-flop, like all digital circuits, has a delay from the active edge of the clock to its output changing. So each clock pulse coming in causes a change that ripples through the chain of flip-flops. This is why we call these ripple counters. Observed on a human time scale, this ripple looks instantaneous, but at the circuitry level, those delays could have unpleasant effects since the values on all the outputs are not consistent until the final one has updated. They are simple, but the ripple effect can be problematic, especially as the chain of flip-flops gets longer.
That said, they are simple and effective. In cases where the ripple effect isn't a problem, they can be a good solution.
To avoid the latency inherent in the design of a ripple counter, we need to have all the flip-flops update at the same time. That means having them all use the same clock signal. As usual, solving a problem isn't without cost. In this case (indeed in many cases in digital circuit design) this takes the form of more circuitry. Since all flip-flops are being clocked at the same time, rather than the clock rippling through, we need to add some logic to control when each flip-flop toggles. Below is a 4-bit synchronous counter. Compare it to the 4-bit ripple counter above.
Each flip-flop only toggles when all the flip-flops to the left (i.e. lower place values) have a state of 1.
Counting in binary is great, but sometimes we just don't want to count to a power of two before looping. We may want to count 0-9 and repeat. We know that will need 4 bits, but we need to go back to zero before the counter naturally would.
The 7490 is one counter that we can use to make a 0-9 counter. The logic symbol makes it look simple enough.
There are a couple each of active high set (MS) and reset/clear (MR) inputs that are ANDed (e.g. both MR inputs have to be high to clear the counter). As expected, there are 4 Q outputs. The odd bit is the two clock inputs. We need to take a look inside to see what that's all about.
As you can see, the set and reset connects to all 4 flip-flops. But other than that, the first/left-most/lowest-place flip-flop is separate from the other three. To make a 0-9 counter, Q0 is connected to /CP1, and /CP0 is the clock input. Notice that some of the J and K inputs aren't connected in the diagram; they can be assumed to be always at logic 1.
The final interesting thing is that the rightmost flip-flop is an R-S, unlike the other J-Ks. And it's clock is syncronous with the Q1 flip-flop, while clocks to the Q1 and Q2 flip-flops ripple (assuming Q0 is connected to /CP1).
Assuming all flip-flops start with a 0 state, trace through the circuit and figure out what happens on each of the next 10 clock pulses. Record the values of the various signals at each state in a truthtable like the one below. All clocks are active on their falling edge.