A demultiplexer is very much like a decoder with an enable. The idea is that you select one of the outputs and route an input signal to it. In fact the 74139 1-of-4 decoder in the previous section is also known as a 1-of-4 demultiplexer. When the E input is high, the selected output is high (ok, they all are but that's not the point). When E is low, the selected output is low. The E input is effectively routed to the selected output. If E varies over time, the selected output will vary in the same way.
Below is the logic diagram of the internals of one of the demultiplexers, as we've seen before. You can see that the enable (we can think of it as the data input for the demultiplexer) feeds into all of the output gates. Each of those NAND gates detect one of the possible patterns on the A inputs, and hence one of the 4 outputs to which the enable/data input is routed.
It's interesting to note that the enable/data input is immediately inverted and that NAND gates are used to generate the outputs. What's happening is that the logic is done in an active-high way, with the input and outputs inverted to externally be active-low. Even more interesting is that the A inputs are also immediately inverted, then inverted again. Recall the previous diagram where the normal and inverted inputs are used to select the various patterns (since for a given pattern, all inputs to the matching AND gate must be high, so the negated form of any that need to be low is used). But why the double negation? That is more of an implementation issue. You know how you'll see that an microcontroller GPIO pin can supply up to some number of milliamps and you can drive an LED directly but you need to do something special to drive a high current load (like a relay or motor)? That's what's going on here. Each input requires a certain amount of current. Chip designers try very had to ensure that each input of a chip presents only a single load to whatever it is connected to. Each output can provide enough current to drive a certain number of input loads, noted as it's fan-out. Negating each input as above ensure that it only presents a single load. Otherwise it would present 3: a NOT gate input and 2 AND gate inputs. When you design logic circuits you need to keep track of how many inputs are connected to each output so as not to exceed each output's fan-out. If you ignore that your circuit could work strangely or not at all.
Multiplexers are the opposite of demultiplexers: they route a selected input to a single output.
The 74153 is typical of a multiplexer. It is, in fact, a dual 4-input multiplexer. The two halves aren't completely independent, though: they share input selection inputs. Each multiplexer does have its own enable signal.
If we look inside, we can see how it works.
Here the data inputs are named I0a-I2a and I0b-I3b. The a inputs selectively get routed to Za, and the b inputs get routed to Zb.
The signal group S selects which input gets routed to the output, for each of the two multiplexers.
Finally, each side has its own active low enable input, when it's low the routed input appears on the output, when it's high the output is low. Unlike recent circuits, this one is active high.
Notice the use of the AND-OR combination that I wrote about in Digital Circuits 1.