The two kinds of ADC architecture most commonly used today are the Successive Approximation Register (SAR) and the Sigma-Delta.
There are several ways to build a SAR, but the simplest uses a comparator and a DAC:
The process starts by setting the DAC's most significant bit to 1, which sets the DAC's output voltage to half its maximum output voltage. If the input is higher than the DAC's output, the comparator's output will be 1. If the input is lower than the DAC's output, the comparator's output will be 0.
The SAR copies the comparator's output to the DAC's MSB, sets the DAC's next most significant bit to 1, and does the whole thing again. On the second pass the DAC's output only changes by a quarter of its maximum value, on the third pass it changes by an eighth, and so on.
If you're familiar with computer algorithms, a SAR does the hardware equivalent of a binary search.
When the DAC runs out of bits, the SAR has finished its approximation of the input voltage, and returns the DAC setting as output.
The capacitor at the left, with all the switches around it, is called the flying capacitor. The capacitor on the right, at the input of the comparator, is called the summing capacitor. The summing cap is usually much larger than the flying cap.
The switches around the flying cap are controlled by the clock and the comparator's output. The schematic above looks complicated because it shows several possible connections all at once.
When the clock is low, the connections simplify to this:
The flying capacitor charges to a predetermined voltage called Vdelta, while the comparator decides whether the summing cap's voltage is higher or lower than the input voltage. That decision is stored as the value S.
There are two possible sets of connections once the clock goes high.
If the clock is high and S is high, the connections simplify (almost) to this:
NOTE: I've removed the connection between the flying capacitor and the summing capacitor to make the flying cap's job easier to understand.
The voltage buffer (bottom center) copies the voltage at the top of the summing capacitor (Vcap). The negative end of the flying cap connects to that, which would put the positive end of the flying capacitor at Vcap + Vdelta if there was no connection to the summing cap.
In fact, the flying cap does connect to the summing cap, and dumps its charge into the summing cap. The capacitors reach equilibrium when the flying cap's voltage is 0V and the summing cap's voltage is slightly higher than it was before.
At the same time, the counter that tracks the number of times S is high increases by 1.
If the clock is high and S is low, the connections simplify (almost) to this:
This time the positive end of the flying cap is connected to the voltage buffer, and the negative end's voltage would be Vcap - Vdelta without a connection to the summing cap. In fact, the flying cap's voltage drops to 0V and the summing cap's voltage decreases slightly.
At the same time, the counter that tracks the number of times S is low increases by 1.
As long as the summing cap's voltage is lower than the input voltage, S will stay high and the 'S is high' counter will increase while the 'S is low' counter doesn't. The opposite is true as long as the summing cap's voltage is lower than the input: S stays low, and the 'S is low' counter advances while the 'S is high' counter doesn't.
Eventually the summing cap's voltage will get close enough to the input voltage that S changes with every tick of the clock: adding charge from the flying cap makes the summing cap voltage higher than the input, subtracting charge from the flying cap makes the summing cap voltage lower than the input, and both counters advance at the same rate.
Subtracting the 'S is low' counter from the 'S is high' counter, then multiplying the result by Vdelta and the size of the flying cap tells us the amount of charge in the summing cap. Dividing that by the size of the summing cap tells us the summing cap's voltage (and the input voltage).
Mathematically, we use the symbol Sigma to represent the sum of a series. We use the symbol Delta to represent a small change. Putting them together as Sigma-Delta means 'the sum of a series of small changes', which describes what the ADC does.
A SAR can usually collect samples faster than a Sigma-Delta ADC with the same resolution. The SAR only needs N steps to approximate 2N possible values, while the Sigma-Delta might need to count several thousand pulses of the flying cap.
A SAR also creates less noise in the circuit around it. Changing a DAC's output voltage doesn't require much current, and the changes get smaller and smaller with each step. A Sigma-Delta has to charge the flying cap over and over again, and needs a fast clock, both of which create sudden changes in the current load. It's been said that SARs are analog circuits that happen to produce digital output, while Sigma-Deltas are digital circuits whose output has a coincidental relationship with some analog voltage.
Sigma-Deltas have the strong advantage that input-referred Gaussian noise makes them work better.
When the summing cap's voltage is close to the input voltage, and the value of S is supposed to change with every tick of the clock, noise will push the summing cap's voltage a little higher or lower. Occasionally the voltage will change enough to make S stay high or low for more than one tick as the flying cap gets rid of the noise voltage.
If the input voltage is only slightly below Vcap, there's a good chance that noise will make Vcap stay higher than the input for more than one tick of the clock. The opposite is true if the input voltage is only slightly higher than Vcap. The two counters won't advance at the same average rate until Vcap‘s voltage is halfway between the next-higher and next-lower voltages around it.
That combination of (relative) simplicity, ability to use noise, and almost unlimited resolution makes Sigma-Delta ADCs popular.
When it comes to applications, SARs tend to be more popular for jobs that require a high sampling rate and low-to-moderate resolution. Sigma-Deltas tend to be more popular for jobs that can tolerate a lower sampling rate but need higher resolution.